The present invention relates to a resource management device in a data processing system in which a plurality of masters access a shared resource.
In recent years, a small chip area, low power consumption, and capability of effective processing have become critical in a system LSI in which a plurality of masters, such as processors, DSPs (Digital Signal Processors), DMA (Direct Memory Access) controllers, etc., are connected to a resource, such as a memory, an input/output device, etc., by way of a plurality of buses. To that end, it is important to share the resource and realize effective access control.
In access control for enabling the resource sharing, the right to use the resource needs to be arbitrated in order to prevent a collision of access requests transmitted from the masters. Since the access conditions vary from master to master, the arbitration operation has to be performed flexibly so as to correspond to the access conditions of each master. Conventional access management devices which perform flexible arbitration are as follows.
A first conventional technique is a bus arbitration system for arbitrating accesses from a plurality of input/output devices to a single bus. In this system, a device having the highest priority is switched at a certain time interval, and when the highest priority device does not use the bus or for a period of time in which no highest priority device is specified, the arbitration operation is performed based on a fairly-allocated round-robin scheme or the like (see U.S. Pat. No. 5,533,205).
According to a second conventional technique, an access bandwidth is guaranteed in accesses from a plurality of masters to a shared resource by pre-allocating the access from each master (see U.S. Pat. No. 5,948,089).
A third conventional technique is a bus arbitration system for controlling accesses from a plurality of masters to a single bus. In this system, priority order is changed at every bus cycle, which is the unit cycle of bus operation, so that the right to use the bus only for the next single bus cycle unit is given (see U.S. Pat. No. 6,070,205).
In the first conventional technique, it is possible to set a time at which each device is assigned the highest priority for using the bus. However, in a case where a bus cycle in which the bus is used requires a plurality of clocks, the access, once it has started, does not stop even if the device having the highest priority is switched to another device, which inhibits access from the device that should be arbitrated with the highest priority.
In the second conventional technique, it is possible to allocate the bus for a suitable period of time in accordance with accesses made from the masters. Nevertheless, when an access request sent from each master is unpredictable, the allocation of the right to use the shared resource to each maser cannot be performed properly.
In the third conventional technique, it is possible to assign weights to the allocation of the bus-use right to the masters. However, when bus cycles with different transfer sizes are present together or when access time to the resource changes depending upon circumstances, a transfer size within a given time period and hence an access bandwidth cannot be guaranteed for each master, because each bus cycle has a different number of clocks.